
Specifications PCI-DAS1602/16
Counter
*Note: Pins 21, 24, and 25 are pulled to logic high via 10K resistors.
Table 11. Counter specifications
Counter type 82C54
Configuration Two 82C54 chips containing three 16-bit down counters each
82C54A:
Source: ADC Clock.
Gate: Programmable source.
Counter 0 — ADC residual sample
counter.
Output: End-of-Acquisition interrupt.
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Counter 1 — ADC pacer lower
divider
Output: Chained to Counter 2 Clock.
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Counter 2 — ADC pacer upper
divider
Output: ADC Pacer clock (if software selected), available at user
connector.
82C54B:
Source: ADC Clock.
Gate: External trigger
Counter 0 — pretrigger mode
Output: End-of-Acquisition interrupt.
Source: User input at 100pin connector or internal 10MHz (software
selectable)
Gate: User input at 100pin connector.
Counter 0 — non-pretrigger mode:
user counter 4
Output: Available at 100pin connector.
Source: 10 MHz oscillator
Gate: Tied to Counter 2 gate, programmable source.
Counter 1 — DAC pacer lower
divider
Output: Chained to Counter 2 Clock.
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Counter 2 — DAC pacer upper
divider
Output: DAC Pacer clock, available at user connector.
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input high 2.0 volts min, 5.5 volts absolute max
Input low 0.8 volts max, -0.5 volts absolute min
Output high 3.0 volts min @ -2.5 mA
Output low 0.4 volts max @ 2.5 mA
Crystal oscillator frequency 10 MHz
Frequency accuracy 50 ppm
6
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