MC PCI-DAS1602 Bedienungsanleitung

PCI-DAS1602/12PCI Bus Data Acquisition BoardUser’s ManualRevision 4, September 2001MEASUREMENT COMPUTING CORPORATION

Figure 3-3. Pin Translation - Pins 51-100 to Pins 1-50, Digital I/O Signals6

4.0 ANALOG CONNECTIONS4.1 ANALOG INPUTSAnalog signal connection is one of the most challenging aspects of applying a data acquisition board. Ifyou ar

Differential InputsDifferential inputs measure the voltage between two distinct input signals. Within a certain range (referredto as the common mode r

Before moving on to the discussion of grounding and isolation, it is important to explain the concepts ofcommon mode, and common mode range (CM Range)

Which system do you have?Try the following experiment. Using a battery powered voltmeter*, measure the voltage (difference)between the ground signal a

The most frequently encountered grounding scenario involves grounds that are somehow connected, buthave ac and/or dc offset voltages between the PCI-D

4.2 WIRING CONFIGURATIONSCombining all the grounding and input type possibilities provides us with the following potential connectionconfigurations. T

4.2.2 Common Ground / Differential InputsThe use of differential inputs to monitor a signal source with a common ground is an acceptable configura-tio

4.2.5 Common Mode Voltage > +/-10V The PCI-DAS1602/12 will not directly monitor signals with common mode voltages greater than +/-10V.You will ne

4.2.6 Isolated Grounds / Single-Ended InputsSingle-ended inputs can be used to monitor isolated inputs, though the use of the differential mode willin

LIFETIME WARRANTYEvery hardware product manufactured by Measurement Computing Corp. is warranted against defects inmaterials or workmanship for the li

5.0 PROGRAMMING & APPLICATIONSYour PCI-DAS1602/12 is supported by Measurement Computing’s powerful Universal Library. Westrongly recommend that y

6.0 SELF-CALIBRATION The PCI-DAS1602/12 is shipped fully-calibrated from the factory with calibration coefficients stored innvRAM. At run time, thes

The calibration scheme for the Analog Out section is shown in Figure 6-2 below. This circuit is duplcatedfor both DAC0 and DAC112RefDACAnalog OutOffs

7.0 REGISTER DESCRIPTION 7.1 REGISTER OVERVIEWPCI-DAS1602/12 operation registers are mapped into I/O address space. Unlike ISA bus designs, thisbo

WRITEINT0INT1INTEDAHFIEEOAIEDAHFCLEOACLINTCL----DAEMIEADFLCLDAEMCL-0123456789101112131415Write operations to this register allow the user to select in

DAEMCLA write-clear to reset DAEM interrupt status.1= Clear DAEM interrupt.0 = No effect.NOTE: It is not necessary to reset any write-clear bits afte

0 = Indicates non-overflow condition of ADC FIFO.DAEMIStatus bit of DAC FIFO Empty interrupt. Used to indicate that a FIFO'd DAC operation has

305 µV80 to 1.25 V111610 µV40 to 2.5 V0111.22 mV20 to 5 V1012.44 mV10 to10 V001610 µV8±1.25 V1101.22 mV4±2.5 V0102.44 mV2± 5 V1004.88 mV1±10 V000Measu

TS[1:0]These bits select one-of-three possible ADC Trigger Sources:External (Analog)11External (Digital)01Software Trigger10Disabled00SourceTS0TS1Note

0 = No Effect.HI_EN,These bits select the Analog Trigger/Gate Mode as described in the table below.CLO_EN,Note that the CHI Threshold is set by DAC1,

Table of Contents378.0 SPECIFICATIONS ...367.6.2 DAC FIFO CLEAR REGISTER...

C0SRCThis bit allows the user to select the clock source for user Counter 0. 1 = Internal 10 MHz oscillator0 = External clock source input via CTR0CL

CSRC[2:0] These bits select the different calibration sources available to the ADC front end.VDAC1111VDAC00118.6mV1010.875V0011.75V1103.5V0107.0V10

DAPS[1:0]These bits select the DAC Pacer Source:External Rising Edge11External Falling Edge01Internal 82C54Programmed via BADR3 + 9, + A10SW Convert0

7.4 BADR2The I/O Region defined by BADR2 contains the ADC Data register and the ADC FIFO clear register.7.4.1 ADC DATA REGISTERBADR2 + 0 ADC Data regi

7.5 BADR3The I/O Region defined by BADR3 contains data and control registers for the ADC Pacer, DAC Pacer,Pre/Post-Trigger Counters and Digital I/O by

8254A COUNTER 2 DATA - ADC PACER DIVIDER UPPERBASE + 2READ/WRITED0D1D2D3D4D5D6D701324567Counter 1 provides the lower 16 bits of the 32-bit pacer cloc

D0D1D2D3D4D5D6D701324567DIO PORT B DATABADR3 + 5PORT B can be configured as an 8-bit input or output channel. Functionality is the same as PORT A.REA

1559BININININ11111549AOUTINININ011115399INOUTININ101115298OUTOUTININ001114793ININOUTIN110114692OUTINOUTIN010114591INOUTOUTIN100114490OUTOUTOUTIN000113

8254B COUNTER 1 DATA - DAC PACER DIVIDER LOWER BADR3 + 9READ/WRITED0D1D2D3D4D5D6D7013245678254B COUNTER 2 DATA - DAC PACER DIVIDER UPPERBADR3 + Ah

7.6.1 DAC DATA REGISTERBADR4 + 0 DAC Data register. A Write-only register.WRITEDA0DA1DA2DA3DA4DA5DA6DA7DA8DA9DA10DA1100000123456789101112131415 MS

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7.6.2 DAC FIFO CLEAR REGISTERBADR4 + 2The DAC FIFO Clear register is a write-only register. A write to this address location clears the DACFIFO. Dat

8.0 SPECIFICATIONS Typical for 25°C unless otherwise specified. POWER CONSUMPTIONTable 1. Power Consumption30 mA maximum+12V1.2A typical, 1.5A ma

ACCURACY – ANALOG INPUTS330 kHz sampling rate, single channel operation and a 60-minute warm-up: Accuracies are listed foroperational temperatures wit

Noise PerformanceTable 6 below summarizes the noise performance for the PCI-DAS1602/12. Noise distribution is deter-mined by gathering 50K samples @ 3

Table 9 – Accuracy Components (errors in LSBs)±1.0 max±1.0 max±0.4 max±2.0 max0 to +5.000V±1.0 max±1.0 max±0.2 max±2.0 max0 to +10.00V±1.0 max±1.0 max

INTERRUPTSTable 12. InterruptsExternal (rising TTL edge event)Residual sample counterA/D end of conversionA/D end of channel scan A/D FIFO-not-empty A

10 MHzCrystal Oscillator Frequency0.4 volts max @ 2.5mAOutput Low3.0 volts min @ −2.5mAOutput High0.8 volts max, −0.5 volts absolute minInput Low2.0 v

Table 18. 8-Channel Differential Mode Pin OutGND100GND50EXTERNAL INTERRUPT99SSH OUT49N/C98PC +5V48EXTERNAL D/A PACER GATE97N/C47D/A INTERNAL PACER OU

Table 19. 16-Channel Single-Ended Mode Pin OutGND100GND50EXTERNAL INTERRUPT99SSH OUT49N/C98PC +5V48EXTERNAL D/A PACER GATE97N/C47D/A INTERNAL PACER O

EC Declaration of ConformityWe, Measurement Computing Corp., declare under sole responsibility that the product:DescriptionPart NumberHigh speed anal

1.0 INTRODUCTION 1.1 FUNCTIONAL DESCRIPTIONThe PCI-DAS1602/12 multifunction analog and digital I/O board sets a new standard for high performancedat

Measurement Computing Corporation16 Commerce Boulevard,Middleboro, Massachusetts 02346(508) 946-5100Fax: (508) 946-9500E-mail: info@measurementcomputi

1.1.3 Analog OutputsThe PCI-DAS1602/12 provides two channels of high-speed 12-bit analog output. The analog outputs areupdated via an on-board FIFO a

2.0 INSTALLATION2.1 SOFTWARE INSTALLATIONIn order to easily test your installation, it is recommended that you install InstaCal the installation, cal

Analog Ground 1Analog Input Ch 0 High 2Analog Input Ch 0 Low / 8 High 34567891011121314151617 Analog Ground 18NC 19202122

CIO-MINI50 or DIGITAL SIGNAL CONDITIONINGANALOG SIGNALCONDITIONING orCIO-MINI50C100FF-XXCABLEPCI-DAS1602/12100-Pin ConnectorANALOG I/OPINS 1 TO 50DIGI